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2010•Unpublished venueRequires access

Programmable Digital Front-End Design for Software Defined Radio

Lin Fei-yu, Qiao Wei-ming, Jianchuan Zhang, Nan Gang-yang, Li Wei-bin, Mao Wei-yu

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Abstract

The incoming evolution from 2G to 3G and beyond requires multimode operation of wireless communication system. In order to cope with these requirements, flexible and highly optimized digital signal processing has received growing interest. In this paper, a digital front-end (DFE) architecture for software defined radio (SDR) is introduced. The system comprises of cascade of filters including economical fractional rate-change ones. All modules in the DFE are programmable. The system has been designed on Xilinx Virtex-5 XC5VSX50T FPGA device with a decimation factor ranged from 1 to 8192. And the maximum bandwidth of the DFE is 2.9Mhz.Design details and trade-offs are also described.

About this research paper

What this paper is about

The incoming evolution from 2G to 3G and beyond requires multimode operation of wireless communication system. In order to cope with these requirements, flexible and highly optimized digital signal processing has received growing interest. In this paper, a digital front-end (DFE) architecture for software defined radio (SDR) is introduced. The system comprises of cascade of filters including economical fractional rate-change ones. All modules in the DFE are programmable. The system has been designed on Xilinx Virtex-5 XC5VSX50T FPGA device with a decimation factor ranged from 1 to 8192. And the maximum bandwidth of the DFE is 2.9Mhz.Design details and trade-offs are also described.

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Available abstract

The incoming evolution from 2G to 3G and beyond requires multimode operation of wireless communication system. In order to cope with these requirements, flexible and highly optimized digital signal processing has received growing interest. In this paper, a digital front-end (DFE) architecture for software defined radio (SDR) is introduced. The system comprises of cascade of filters including economical fractional rate-change ones. All modules in the DFE are programmable. The system has been designed on Xilinx Virtex-5 XC5VSX50T FPGA device with a decimation factor ranged from 1 to 8192. And the maximum bandwidth of the DFE is 2.9Mhz.Design details and trade-offs are also described.

Key concepts: Software-defined radio, Decimation, Field-programmable gate array, Computer science, Front and back ends, Bandwidth (computing), Digital radio, Embedded system

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