2007Unpublished venueRequires access

Multiband direct RF-sampling receiver front-end for WLAN in 0.13 μm CMOS

Stefan Andersson, Rashad Ramzan, Jerzy Dąbrowski, Christer Svensson

Open publisher page 4 citations

Abstract

In this paper a flexible RF-sampling front-end primarily intended for WLAN operating in the 2.4 GHz and 5- 6 GHz bands is presented. The circuit is implemented in a 0.13 mum CMOS process with certain built-in test features. It consists of a wideband LNA and a SC discrete-time decimation filter used as a sampling IQ down-converter. The architecture is generic and scalable in frequency and it can operate at a sampling frequency up to 3 GHz and RF carrier up to 6 GHz. The decimation factor is 8 or 16 rendering the following A/D conversion feasible. The frequency response, linearity, and NF of the whole front-end have been measured. At the power consumption of 176 mW the circuit achieves specs that are satisfactory for WLAN applications.

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What this paper is about

In this paper a flexible RF-sampling front-end primarily intended for WLAN operating in the 2.4 GHz and 5- 6 GHz bands is presented. The circuit is implemented in a 0.13 mum CMOS process with certain built-in test features. It consists of a wideband LNA and a SC discrete-time decimation filter used as a sampling IQ down-converter. The architecture is generic and scalable in frequency and it can operate at a sampling frequency up to 3 GHz and RF carrier up to 6 GHz. The decimation factor is 8 or 16 rendering the following A/D conversion feasible. The frequency response, linearity, and NF of the whole front-end have been measured. At the power consumption of 176 mW the circuit achieves specs that are satisfactory for WLAN applications.

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Available abstract

In this paper a flexible RF-sampling front-end primarily intended for WLAN operating in the 2.4 GHz and 5- 6 GHz bands is presented. The circuit is implemented in a 0.13 mum CMOS process with certain built-in test features. It consists of a wideband LNA and a SC discrete-time decimation filter used as a sampling IQ down-converter. The architecture is generic and scalable in frequency and it can operate at a sampling frequency up to 3 GHz and RF carrier up to 6 GHz. The decimation factor is 8 or 16 rendering the following A/D conversion feasible. The frequency response, linearity, and NF of the whole front-end have been measured. At the power consumption of 176 mW the circuit achieves specs that are satisfactory for WLAN applications.

Key concepts: Decimation, RF front end, CMOS, Front and back ends, Electronic engineering, Sampling (signal processing), Electrical engineering, Wideband

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