A distance reduction approach to design for testability

The average distance between states is proposed as a new testability measure for finite state machines (FSMs). Also proposed is the concept of center state to reduce distances in FSMs. This test function embedding technique has been shown to improve the testability of sequential circuits with minimal overhead. An overview of several design for testability (DFT) and synthesis for testability (SFT) methods for sequential circuits is also given in this paper. Experimental results have shown that DFT approach is more advantageous than SFT approach to implement our test function. The contribution of this paper is to analyze the trade-offs between several aspects of DFT and SFT techniques.