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1999•IEEE Transactions on Consumer ElectronicsRequires access

An FPGA prototype of a forward error correction (FEC) decoder for ATSC digital TV

Hung‐Yu Yang, Yan Zhong, Leijing Yang

Open publisher page 8 citations

Abstract

The paper presents the development of an FEC decoder for ATSC digital TV. An FEC encoder/decoder system has been first built up for studying the performance of the FEC decoder and also for providing testing vectors for the architecture design. The architecture of the FEC decoder, including trellis decoder, de-interleaver, Reed-Solomon (RS) decoder and de-randomizer is then designed. The decoder has been prototyped in FPGAs and verified using an FPGA board. The FEC decoder can achieve the threshold of visibility (TOV) at 14.9 dB and 18.8 dB in the cases without and with NTSC rejection filter respectively.

About this research paper

What this paper is about

The paper presents the development of an FEC decoder for ATSC digital TV. An FEC encoder/decoder system has been first built up for studying the performance of the FEC decoder and also for providing testing vectors for the architecture design. The architecture of the FEC decoder, including trellis decoder, de-interleaver, Reed-Solomon (RS) decoder and de-randomizer is then designed. The decoder has been prototyped in FPGAs and verified using an FPGA board. The FEC decoder can achieve the threshold of visibility (TOV) at 14.9 dB and 18.8 dB in the cases without and with NTSC rejection filter respectively.

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OpenAlex reports 8 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

The paper presents the development of an FEC decoder for ATSC digital TV. An FEC encoder/decoder system has been first built up for studying the performance of the FEC decoder and also for providing testing vectors for the architecture design. The architecture of the FEC decoder, including trellis decoder, de-interleaver, Reed-Solomon (RS) decoder and de-randomizer is then designed. The decoder has been prototyped in FPGAs and verified using an FPGA board. The FEC decoder can achieve the threshold of visibility (TOV) at 14.9 dB and 18.8 dB in the cases without and with NTSC rejection filter respectively.

Key concepts: Forward error correction, Computer science, Soft-decision decoder, Field-programmable gate array, Encoder, NTSC, Trellis (graph), Computer hardware

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