Heuristics for context-caches in 2-level reconfigurable architectures
J. S. Lange, Martin Middendorf
Abstract
J. S. Lange, Martin Middendorf
Abstract
Heuristics for the use of a context cache in multi-context 2-level reconfigurable architectures are proposed. These architectures can be dynamically reconfigured on two different levels. The lower level allows to perform ordinary reconfiguration operations on the reconfigurable resources. On the upper reconfiguration level the reconfiguration capabilities of the reconfigurable resources that are available for the lower level reconfiguration can be reconfigured. We consider 2-level reconfigurable architectures with a cache for contexts that correspond to the upper reconfiguration level. Different heuristics to select the contexts that are stored in the cache are proposed in order to reduce the total reconfiguration costs.
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Heuristics for the use of a context cache in multi-context 2-level reconfigurable architectures are proposed. These architectures can be dynamically reconfigured on two different levels. The lower level allows to perform ordinary reconfiguration operations on the reconfigurable resources. On the upper reconfiguration level the reconfiguration capabilities of the reconfigurable resources that are available for the lower level reconfiguration can be reconfigured. We consider 2-level reconfigurable architectures with a cache for contexts that correspond to the upper reconfiguration level. Different heuristics to select the contexts that are stored in the cache are proposed in order to reduce the total reconfiguration costs.
Key concepts: Control reconfiguration, Computer science, Heuristics, Cache, Context (archaeology), Parallel computing, Computer architecture, Embedded system