A Cost-Effective Dynamic Partial Reconfiguration Implementation Flow for Xilinx FPGA

Reconfigurability of Field Programmable Gate Array (FPGA) makes it one of the most promising approaches in the implementation of reconfigurable systems. Partitioning the reconfigurable system to many Reconfigurable Modules (RMs) and allocating them into Reconfigurable Regions (RRs) on the FPGA is a challenging task for the system designer. Partitioning choices impact the area efficiency and the time of reconfiguration of the reconfigurable systems. In this paper, different partitioning techniques are studied and evaluated according to their impact on reconfiguration time and the area utilization. Also, a new proposed Dynamic Partial Reconfiguration (DPR) tool flow is presented that automates and optimizes the partitioning procedure based on a graph clustering algorithm, modifies the design's HDL files as per the partitioning results, and implements a routing switch to dynamically change routing between Reconfigurable Regions (RRs) during reconfiguration.