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Towards fully integrated SiC cascade power switches for high voltage applications

Andrei Mihăilă, Florin Udrea, Philippe Godignon, Gheorghe Brezeanu, Rajesh Kumar Malhan, Alexandru-Vlad Rusu, José del R. Millán, Gaj Amaratunga

Open publisher page 10 citations

Abstract

This paper presents an advanced numerical analysis of novel hybrid silicon/SiC multiple cascode configuration. The novel approach is exemplified through a three device cascode Configuration, whereby a 5-20V silicon MOSFET blocks a lateral medium voltage 60-100V SiC JFET, which in turn reverse biases the gate of a vertical high voltage (/spl ges/1.2kV) SiC JFET. Furthermore, an elegant solution for the SiC part of the hybrid multiple cascode is also presented. A fully integrated SiC cascoded JFETs chip is proposed and numerically demonstrated. The results obtained through mixed mode simulations for the two cascode configurations are compared.

About this research paper

What this paper is about

This paper presents an advanced numerical analysis of novel hybrid silicon/SiC multiple cascode configuration. The novel approach is exemplified through a three device cascode Configuration, whereby a 5-20V silicon MOSFET blocks a lateral medium voltage 60-100V SiC JFET, which in turn reverse biases the gate of a vertical high voltage (/spl ges/1.2kV) SiC JFET. Furthermore, an elegant solution for the SiC part of the hybrid multiple cascode is also presented. A fully integrated SiC cascoded JFETs chip is proposed and numerically demonstrated. The results obtained through mixed mode simulations for the two cascode configurations are compared.

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OpenAlex reports 10 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

This paper presents an advanced numerical analysis of novel hybrid silicon/SiC multiple cascode configuration. The novel approach is exemplified through a three device cascode Configuration, whereby a 5-20V silicon MOSFET blocks a lateral medium voltage 60-100V SiC JFET, which in turn reverse biases the gate of a vertical high voltage (/spl ges/1.2kV) SiC JFET. Furthermore, an elegant solution for the SiC part of the hybrid multiple cascode is also presented. A fully integrated SiC cascoded JFETs chip is proposed and numerically demonstrated. The results obtained through mixed mode simulations for the two cascode configurations are compared.

Key concepts: JFET, Cascode, Voltage, MOSFET, Materials science, Cascade, Electrical engineering, Silicon carbide

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