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True single phase clock dynamic CMOS circuit technique

Ingrid Karlsson

Open publisher page 48 citations

Abstract

Some CMOS circuit techniques, based on a true single-phase clock, where the clock is never inverted, are described. Single-phase dynamic logic and single-phase precharge logic circuits are considered. The advantage of this approach is simple and compact clock distribution and high speed. The high-speed possibility was demonstrated with a binary divider. A clock frequency of 160 MHz was achieved when only standard transistors in a 3- mu m CMOS process were used. The single-phase clock is relatively insensitive to clock rise time, clock fall time, and clock skew.>

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What this paper is about

Some CMOS circuit techniques, based on a true single-phase clock, where the clock is never inverted, are described. Single-phase dynamic logic and single-phase precharge logic circuits are considered. The advantage of this approach is simple and compact clock distribution and high speed. The high-speed possibility was demonstrated with a binary divider. A clock frequency of 160 MHz was achieved when only standard transistors in a 3- mu m CMOS process were used. The single-phase clock is relatively insensitive to clock rise time, clock fall time, and clock skew.>

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Available abstract

Some CMOS circuit techniques, based on a true single-phase clock, where the clock is never inverted, are described. Single-phase dynamic logic and single-phase precharge logic circuits are considered. The advantage of this approach is simple and compact clock distribution and high speed. The high-speed possibility was demonstrated with a binary divider. A clock frequency of 160 MHz was achieved when only standard transistors in a 3- mu m CMOS process were used. The single-phase clock is relatively insensitive to clock rise time, clock fall time, and clock skew.>

Key concepts: Clock skew, Digital clock manager, Clock domain crossing, Clock gating, Synchronous circuit, CPU multiplier, Asynchronous circuit, Clock signal

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