應用於60-GHz CMOS毫米波射頻接收機前端電路之研製

This thesis presents the design on CMOS RFICs for 60-GHz millimeter-wave wireless receiver RF front-end. The RFICs are fabricated with TSMC CMOS 0.13 μm 1P8M and TSMC CMOS 0.18 μm 1P6M standard processes. In the first part of the thesis, we introduce the millimeter-wave for short-range high data-rate WPAN applications and a brief chronology of the 60-GHz standardization activity. The block diagrams and link budget of the 60-GHz WPAN system are also discussed. The second part of this thesis presents the design and measurement of CMOS RFICs for 60-GHz millimeter-wave RF front-end. First of all, a three-stage cascaded common source LNA is presented. The LNA has demonstrated a gain of 11.7 dB and a minimum noise figure of 7.9 dB at 50 GHz. The total power consumption is 21.6 mW from a 1.2 V power supply. Compared to the other works using 0.13 μm CMOS, this work has shown that the LNA reduces power consumption successfully. In addition, a 20-GHz CMOS 0.18-μm low voltage dual-gate mixer and a 60-GHz CMOS 0.13-μm millimeter-wave dual-gate mixer are proposed. In order to improve port-to-port isolation, a LC series resonator is designed to bypass the LO signal. On other hand, the 60-GHz CMOS millimeter-wave dual-gate mixer has a conversion loss of 2.7 dB and a SSB NF of 21.5 dB. The total power consumption is 16.8 mW from a 1.2 V power supply. Reasonable agreements of the S-parameters and the conversion loss between simulation and measurement were obtained. Finally, a 60-GHz CMOS 0.13-μm millimeter-wave RF receiver front-end is presented. The measurement shows a maximum conversion gain of 12.7 dB at 47 GHz. The 3-dB bandwidth is 4 GHz. The receiver front-end draws 36.4 mA from a 1.2 V power supply. Although there is 13 GHz frequency offset between simulation and measurement, it is feasible to implement a 60-GHz RF receiver front-end using CMOS 0.13-μm process.