A fault model for VHDL descriptions at the register transfer level

This paper presents a fault model for VHDL descriptions at the Register Transfer Level and its evaluation with respect to a logic level fault model (single-stuck-at). The proposed fault model may be used for early estimations of the fault coverage before the synthesis is made in the design process of an integrated circuit. The obtained results show a high correlation between the fault coverages achieved with the proposed fault model and logic fault models on a set of examples. The main contribution of this work is the proposal of a new fault model for VHDL/RT descriptions and the demonstration of its usefulness for estimating the achieved fault coverage with a set of test vectors in design phases previous to synthesis.