RTL fault modeling

Testing of digital circuits has traditionally been done using fault models at the gate level or below. Use of these lower level fault models adds complexity and delays testing efforts to later in the design cycle. There is a need to develop a design methodology for performing fault simulation throughout the design process, at many levels of abstraction. This work focuses on fault modeling and simulation at the register transfer (RT) level, and aims at exploring the capabilities of the stuck-at fault model in computing the fault coverage at the RT-level. The experimental results presented in this paper indicate that fault coverage obtained using RTL level fault modeling has resulted in a coverage that is in close proximity with the corresponding gate-level fault coverage.