A new low power BIST methodology by altering the structure of linear feedback shift registers
Rui Li, Hu Chen, Jun Yang, Zhe Zhang, Youhua Shi, Longxing Shi
Abstract
Rui Li, Hu Chen, Jun Yang, Zhe Zhang, Youhua Shi, Longxing Shi
Abstract
In this paper a new low power BIST methodology effected by altering the structure of linear feedback shift register (LFSR) is proposed. In pseudo-random test mode, the efficiency of the vectors decreases sharply as the test progresses. For low power consumption during test mode, the proposed approach ignores the nondetecting vectors by altering the structure of LFSR. Note that altering the structure of LFSR is efficient, and it has no impact on the fault coverage.
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In this paper a new low power BIST methodology effected by altering the structure of linear feedback shift register (LFSR) is proposed. In pseudo-random test mode, the efficiency of the vectors decreases sharply as the test progresses. For low power consumption during test mode, the proposed approach ignores the nondetecting vectors by altering the structure of LFSR. Note that altering the structure of LFSR is efficient, and it has no impact on the fault coverage.
Key concepts: Linear feedback shift register, Shift register, Built-in self-test, Power consumption, Power (physics), Mode (computer interface), Computer science, Fault coverage