Parasitic-aware Delay Optimization for Multi-GHz Static CMOS Ring Oscillators

A method for optimizing the oscillation frequency of a multi-GHz ring oscillator composed of static CMOS inverters is derived. The derivation is based on the propagation delay of each inverter stage, and it includes the effects of interconnect parasitics and gate resistance. The method was verified with a 90-nm SOI CMOS process through layout extraction and simulation for predicting the underlying factors in delay as the inverter's devices were scaled