Designing highly integrated systems with gigabit/second CMOS serial transceiver cores

Gigabit per second serial interconnects are gaining prominence with the adoption of serial interconnect standards such as Fibre Channel and Gigabit Ethernet. The availability of CMOS transceiver cores allows the system designer to integrate the gigabit physical layer with higher protocol layers, thereby achieving a low cost, low power solution. This paper examines ASIC design with CMOS gigabit transceiver cores, package selection, and board layout considerations for systems employing gigabit per second interconnects.