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A subnanosecond HEMT 1Kb SRAM

K. Nishiuchi, Naoki Kobayashi, S. Kuroda, S. Notomi, Takahiro Nimura, Masayuki Abe, M. Kobayashi

Open publisher page 18 citations

Abstract

HIGH SPEED LSIs have been required for high performance mainframe computers. The development of High Electron Mobility Transistor (HEMT) is felt to be applicable for high-speed logic operation. This paper will report on the design of a 1K x 1b fully static RAM using HEMT. The RAM was constructed with Enhancement/Depletion (E/D) type DCFL circuitry, using 1.5μm gate devices, and 3μm line process.

About this research paper

What this paper is about

HIGH SPEED LSIs have been required for high performance mainframe computers. The development of High Electron Mobility Transistor (HEMT) is felt to be applicable for high-speed logic operation. This paper will report on the design of a 1K x 1b fully static RAM using HEMT. The RAM was constructed with Enhancement/Depletion (E/D) type DCFL circuitry, using 1.5μm gate devices, and 3μm line process.

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OpenAlex reports 18 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

HIGH SPEED LSIs have been required for high performance mainframe computers. The development of High Electron Mobility Transistor (HEMT) is felt to be applicable for high-speed logic operation. This paper will report on the design of a 1K x 1b fully static RAM using HEMT. The RAM was constructed with Enhancement/Depletion (E/D) type DCFL circuitry, using 1.5μm gate devices, and 3μm line process.

Key concepts: High-electron-mobility transistor, Static random-access memory, Transistor, Logic gate, Computer science, Electrical engineering, Process (computing), Electronic engineering

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