An ultra-low voltage digitally controlled low-dropout regulator with digital background calibration

In this paper, we describe a novel ultra-low voltage digitally controlled low-dropout (LDO) voltage regulator offering digitally controllable dynamic voltage scaling (DVS) for near/sub-threshold applications. We eliminate the reference voltage in conventional LDOs and adopt the reference clock that enables the proposed LDO to be controlled digitally. The analog components are replaced by digital counterparts which are able to operate at near/sub-threshold regime. Additionally, a digital background calibration scheme is proposed to minimize the regulated voltage errors due to process, voltage, and temperature (PVL) variations. The proposed LDO has been designed in a 90-nm regular Vt CMOS process and the active area is 0.038-mm2. The LDO can regulate the output voltage from 260-mV to 440-mV, while the input supply voltage is from 380-mV to 500-mV. It delivers 3-mA load current at a 500-mV input and the quiescent current is 30.8-μA. The current and power efficiencies reach 99.0% and 87.1%, respectively. Furthermore, the regulated output voltage of the proposed LDO is tunable digitally in run-time with various step sizes.