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Architectures For A Cordic SVD Processor

Joseph R. Cavallaro, Franklin T. Luk

Open publisher page 20 citations

Abstract

Architectures for systolic array processor elements for calculating the singular value decomposition (SVD) are proposed. These special purpose VLSI structures incorporate the coordinate rotation (coRDic) algorithms to diagonalize 2X 2 submatrices of a large array. The area-time complexity of the proposed architectures is analyzed along with topics related to a prototype implementation.

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What this paper is about

Architectures for systolic array processor elements for calculating the singular value decomposition (SVD) are proposed. These special purpose VLSI structures incorporate the coordinate rotation (coRDic) algorithms to diagonalize 2X 2 submatrices of a large array. The area-time complexity of the proposed architectures is analyzed along with topics related to a prototype implementation.

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Available abstract

Architectures for systolic array processor elements for calculating the singular value decomposition (SVD) are proposed. These special purpose VLSI structures incorporate the coordinate rotation (coRDic) algorithms to diagonalize 2X 2 submatrices of a large array. The area-time complexity of the proposed architectures is analyzed along with topics related to a prototype implementation.

Key concepts: CORDIC, Singular value decomposition, Very-large-scale integration, Computer science, Systolic array, Parallel computing, Rotation (mathematics), Block (permutation group theory)

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