The Characteristics of Hot-Carrier Stressed Bottom-Gate Polycrystalline Silicon Thin-Film Transistors Employing Alternating Magnetic-Field-Enhanced Rapid Thermal Annealing

We have evaluated the reliability of the bottom-gate (BG) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) by employing alternating magnetic-field-enhanced rapid thermal annealing (AMFERTA) under the hot-carrier stress condition. The on-current was reduced due to the trap state creation caused by hot-electrons near drain junction. The off-current was suppressed due to the negative charge trapping near drain junction region. The temperature annealing after hot-carrier stress removed an amount of trap states in the drain junction. However, the tapped negative charges still remained near the drain junction. This charged region acts like lightly doped drain. Therefore, the sufficient annealing condition might be restored to the reduced on-current level without increasing off-current.