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2010•Unpublished venueRequires access

A research of dual-port SRAM cell using 8T

Kai-ji Zhang, Kun Chen, Weitao Pan, Peijun Ma

Open publisher page 7 citations

Abstract

High speed, low power and compatibility with standard technology Static random access memory (SRAM) is essential for system on chip (SoC) technology. In this paper, we first present a 6T-SRAM (1WR) and two types of 8T-SRAM cell(2WR 1W1R). After that how the (1W1R) cell work with external unit is explained, and we compare the SNM sensitivity and the write/read operations time of 1WR 1W1R cell.

About this research paper

What this paper is about

High speed, low power and compatibility with standard technology Static random access memory (SRAM) is essential for system on chip (SoC) technology. In this paper, we first present a 6T-SRAM (1WR) and two types of 8T-SRAM cell(2WR 1W1R). After that how the (1W1R) cell work with external unit is explained, and we compare the SNM sensitivity and the write/read operations time of 1WR 1W1R cell.

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OpenAlex reports 7 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

High speed, low power and compatibility with standard technology Static random access memory (SRAM) is essential for system on chip (SoC) technology. In this paper, we first present a 6T-SRAM (1WR) and two types of 8T-SRAM cell(2WR 1W1R). After that how the (1W1R) cell work with external unit is explained, and we compare the SNM sensitivity and the write/read operations time of 1WR 1W1R cell.

Key concepts: Static random-access memory, Random access memory, Computer science, Compatibility (geochemistry), System on a chip, Chip, Embedded system, Port (circuit theory)

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