2010•Unpublished venueRequires access

1.25/10.3-Gbit/s dual-rate burst-mode receiver with automatic bit-rate discrimination circuit for coexisting PON systems

Kazutaka Hara, S. Kimura, Hirotaka Nakamura, Naoto Yoshimoto, Hisaya Hadama

Abstract

A 1.25-/10.3-Gbit/s parallel-type dual-rate burst-mode receiver with a burst-mode bit-rate discrimination circuit (B-BDC) for coexisting systems is demonstrated. The settling time including B-BDC is less than 250 ns for burst inputs with extremely different powers.

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Key concepts: Burst mode (computing), Gigabit, Settling time, Dual mode, Bit error rate, Bit rate, Bit (key), Electronic engineering