Hierarchical detailed floorplanning with global routing in VLSI layout design

Abstract In a VLSI layout design using the building block approach, the design is divided into two phases, placement and routing. On the other hand, a new hierarchical floorplanning method was proposed by Dai et al., in which a global routing for the evaluation of the placement is determined simultaneously during the design of relative placement. However, the precise estimation of routability is difficult since the global routes in this method do not correspond to the routing region such as channels and switchboxes. In this paper, a new method is proposed, which simultaneously and hierarchically obtains floorplan, shapes and positions of modules, and global routes which directly correspond to switchboxes and channels. In this method, the routing‐based partitioning, the hierarchical detailed global routing, and the hierarchical positioning are repeatedly executed, and a chip with small area and short wire length is obtained. This paper presents these three algorithms, and discusses the experimental results of each algorithm and the whole proposed method in a comparison to the conventional method that separately executes placement and routing.