A sub-1v low-dropout regulator with an on-chip voltage reference

A sub-1V 50 mA low-dropout regulator (LDR) with an on-chip voltage reference is presented. This LDR utilizes the push-pull output stage to reduce the size of the power PMOS transistor. The proposed LDR with the on-chip voltage reference has been fabricated in 0.18 mum CMOS process, and its active area is 0.148 mm2. Experimental results demonstrate that the voltage reference and the LDR work for the supply voltage of 0.6 V~1.2V. For the proposed LDR under a supply of 0.6 V, the measured settling time, voltage dip, and quiescent current are less than 2mus, 50 mV, and 16.6 muA, respectively.