A Framework of High-quality Transition Fault ATPG for Scan Circuits

This paper presents a framework of high-quality test generation for transition faults in full scan circuits. This work assumes a restricted broad-side testing as a test application method for two-pattern tests where control of primary inputs and observation of primary outputs are restricted. Because we use a modified time expansion model of a circuit-under-test during ATPG and fault simulation, conventional ATPG and fault simulation programs can work with minor change. The proposed ATPG method consists of two algorithms, which are activation-first and propagation-first, and for each fault it is decided which algorithm should be applied. Test patterns are generated such that transition faults with small delay can be detected, i.e. a path for fault excitation and propagation becomes as long as possible. In experimental results we evaluate test patterns generated by the proposed method using SDQM that calculates delay test quality, and show the effectiveness of the proposed method