High-drive CMOS buffer for large capacitive loads

A new CMOS buffer circuit for high capacitive loads is presented. The objective of the design is a high-power, area-efficient buffer to be used in very large scale analogue applications. The buffer can deliver a slew rate of 1.2 V/μs to capacitive loads in excess of 5000 pF. It has a total harmonic distortion of less than 3% at 20kHz. At stand by, it consumes only 125 μA (0.625mW). The buffer occupies 100mils2 of die area in a 3 μm technology.