Simultaneous escape routing based on routability-driven net ordering
Jin-Tai Yan, Tung-Yen Sung, Zhiwei Chen
Abstract
Jin-Tai Yan, Tung-Yen Sung, Zhiwei Chen
Abstract
In this paper, given a set of n escape nets between an array of pxq pins and an array of rxs pins, firstly, a routability-driven net order between two given pin arrays is determined for simultaneous escape routing. Furthermore, based on ordered escape routing for two pin arrays, an efficient approach is proposed to solve the routing problem for simultaneous escape routing. Compared with Kong's flow-based approach for three tested examples, the experimental results show that our proposed approach achieves 100% routability for the tested examples and reduces the CPU time by 54.1% on the average.
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In this paper, given a set of n escape nets between an array of pxq pins and an array of rxs pins, firstly, a routability-driven net order between two given pin arrays is determined for simultaneous escape routing. Furthermore, based on ordered escape routing for two pin arrays, an efficient approach is proposed to solve the routing problem for simultaneous escape routing. Compared with Kong's flow-based approach for three tested examples, the experimental results show that our proposed approach achieves 100% routability for the tested examples and reduces the CPU time by 54.1% on the average.
Key concepts: Routing (electronic design automation), Network routing, Net (polyhedron), Parallel computing, Computer science, Set (abstract data type), Topology (electrical circuits), Very-large-scale integration