1983IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsRequires access

Automating Technology Relative Logic Synthesis and Module Selection

Donald E. Thomas, G. W. Leive

Open publisher page 4 citations

Abstract

This paper discusses a design aid which translates the data part of a functional level digital design into a logic level design through the specification of module set information. The constraint driven automatic methodology is discussed and results of using the design aid are presented. Predictors are developed to estimate the logic level design space, thus providing early feedback within the design process.

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What this paper is about

This paper discusses a design aid which translates the data part of a functional level digital design into a logic level design through the specification of module set information. The constraint driven automatic methodology is discussed and results of using the design aid are presented. Predictors are developed to estimate the logic level design space, thus providing early feedback within the design process.

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OpenAlex reports 4 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

This paper discusses a design aid which translates the data part of a functional level digital design into a logic level design through the specification of module set information. The constraint driven automatic methodology is discussed and results of using the design aid are presented. Predictors are developed to estimate the logic level design space, thus providing early feedback within the design process.

Key concepts: Computer science, Selection (genetic algorithm), Logic synthesis, Set (abstract data type), Register-transfer level, Constraint (computer-aided design), Programming language, Logic gate

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