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Multi-level logic synthesis for Concurrent Logic CLi6000 devices

Maureen Pearce, Jonathan Saul, Nlk Lester

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Abstract

Concurrent Logic CLi6000 devices are high granularity, RAM-based reconfigurable FPGAs. The architecture consists of a grid of small cells surrounded by programmable input/output blocks and programmable interconnect. This paper proposes a logic synthesis procedure for complex designs. A register transfer level description of the design can be optimized using multi-level synthesis techniques and then mapped to the FPGA. >

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What this paper is about

Concurrent Logic CLi6000 devices are high granularity, RAM-based reconfigurable FPGAs. The architecture consists of a grid of small cells surrounded by programmable input/output blocks and programmable interconnect. This paper proposes a logic synthesis procedure for complex designs. A register transfer level description of the design can be optimized using multi-level synthesis techniques and then mapped to the FPGA. >

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Available abstract

Concurrent Logic CLi6000 devices are high granularity, RAM-based reconfigurable FPGAs. The architecture consists of a grid of small cells surrounded by programmable input/output blocks and programmable interconnect. This paper proposes a logic synthesis procedure for complex designs. A register transfer level description of the design can be optimized using multi-level synthesis techniques and then mapped to the FPGA. >

Key concepts: Programmable Array Logic, Simple programmable logic device, Register-transfer level, Programmable logic device, Programmable logic array, Computer science, Logic synthesis, Field-programmable gate array

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