A realistic approach to detection test set generation for combinational logic circuits
R.G. Bennetts
Abstract
R.G. Bennetts
Abstract
The paper presents a technique for deriving a detection test set for combinational logic circuits, that is based on the exclusive-OR operator. It is claimed that the procedure is suitable for implementation on a digital computer and this is supported by results relating to single-/multi-output circuits using either basic gates or MSI/LSI logic elements.
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The paper presents a technique for deriving a detection test set for combinational logic circuits, that is based on the exclusive-OR operator. It is claimed that the procedure is suitable for implementation on a digital computer and this is supported by results relating to single-/multi-output circuits using either basic gates or MSI/LSI logic elements.
Key concepts: Combinational logic, Digital electronics, Sequential logic, Computer science, Set (abstract data type), Electronic circuit, Logic gate, Logic optimization