Chip-level and package-level seamless interconnect technologies for advanced packaging

Package-process-oriented thick-Cu-wiring technologies have been developed for forming chip-level and package-level seamless interconnects between an LSI chip and the package substrate. Chip-level seamless interconnects are formed using a resin CMP process. Package-level seamless interconnects are formed by embedding a thinned chip into a resin on Cu base plate. A package with package-level seamless interconnects is thinner and has lower thermal resistance, better power delivery, and finer-pitch interconnects than a conventional flip-chip ball grid array package.