BIST-based digital design for IEEE 1394B PHY

A Built-In Self Test (BIST) based digital design for IEEE 1394b Physical Layer (PHY) is presented. The proposed circuit fabricated in 0.13-μm CMOS technology is mainly composed of 8B/10B encoder/decoder block, I2C slave block, 2nd-order low-pass digital filter, and BIST circuit. This circuit aims at reducing area and power consumption of the chip and meeting the testing needs of IEEE 1394b SerDes PHY, with I2C slave block and BIST system contribute to a more efficient way for chip testing. The die area of the digital circuit is 0.13mm2, and the whole SerDes circuit occupies an area of 2.9×1.6mm2.