ScholarLens Back to search
2002•Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and NanotechnologyRequires access

An Integrated Wafer-Scale Packaging Process for MEMS

Thomas W. Kenny, Rob N. Candler, Huimou J. Li, Woo‐Tae Park, Junghwa Cho, King Ho Holden Li, Aaron Partridge, G. Yama, M. Lutz

Open publisher page 7 citations

Abstract

Packaging is well known to impose significant cost, performance and fabrication constraints on MEMS devices. We have developed a wafer-scale, integrated packaging process which enables a released MEMS device to be sealed within a thick layer of epi-polysilicon. This encapsulation may be tailored to withstand conventional dicing saws, pick/place chip handling equipment, and even high-pressure injection molding for plastic DIP packages. This architecture can be adapted to a variety of MEMS devices, and is compatible with integrated electronics. This paper will describe this packaging technique and discuss applications.

About this research paper

What this paper is about

Packaging is well known to impose significant cost, performance and fabrication constraints on MEMS devices. We have developed a wafer-scale, integrated packaging process which enables a released MEMS device to be sealed within a thick layer of epi-polysilicon. This encapsulation may be tailored to withstand conventional dicing saws, pick/place chip handling equipment, and even high-pressure injection molding for plastic DIP packages. This architecture can be adapted to a variety of MEMS devices, and is compatible with integrated electronics. This paper will describe this packaging technique and discuss applications.

Why it matters

OpenAlex reports 7 citations for this work. Citation counts describe recorded attention and do not establish research quality.

Key contribution

A contribution statement is not available in the OpenAlex record.

Method / approach

Method details are not available in the OpenAlex metadata.

Main findings

Findings are not separately available in the OpenAlex metadata.

Limitations

Limitations are not available in the OpenAlex metadata.

Applications

Application details are not available in the OpenAlex metadata.

Available abstract

Packaging is well known to impose significant cost, performance and fabrication constraints on MEMS devices. We have developed a wafer-scale, integrated packaging process which enables a released MEMS device to be sealed within a thick layer of epi-polysilicon. This encapsulation may be tailored to withstand conventional dicing saws, pick/place chip handling equipment, and even high-pressure injection molding for plastic DIP packages. This architecture can be adapted to a variety of MEMS devices, and is compatible with integrated electronics. This paper will describe this packaging technique and discuss applications.

Key concepts: Wafer dicing, Microelectromechanical systems, Wafer-level packaging, Die preparation, Wafer, Chip-scale package, Wafer-scale integration, Fabrication

Related papers

Related paper 1Related paper 2Related paper 3
Back to paper searchBrowse research topicsOriginal source
An Integrated Wafer-Scale Packaging Process for MEMS — Research Paper | ScholarLens