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Power Characteristics of High Voltage LDMOS Transistors

E. Gebara, Niklas Rorsman, Jörgen Olsson, Herbert Zirath, Klas-Håkan Eklund, Joy Laskar

Open publisher page 9 citations

Abstract

A lateral double diffused DMOS (LDMOS) transistor has been integrated into a CMOS process. An effective RESURF of the drain drift region enables a high breakdown voltage of about 90V and GHz operation. The measured output power density is 1.4W/mm at 1GHz for a supply voltage of 70V. A power added efficiency (PAE) of 51% and an output power density of 1.2W/mm was obtained at 50V.

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What this paper is about

A lateral double diffused DMOS (LDMOS) transistor has been integrated into a CMOS process. An effective RESURF of the drain drift region enables a high breakdown voltage of about 90V and GHz operation. The measured output power density is 1.4W/mm at 1GHz for a supply voltage of 70V. A power added efficiency (PAE) of 51% and an output power density of 1.2W/mm was obtained at 50V.

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OpenAlex reports 9 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

A lateral double diffused DMOS (LDMOS) transistor has been integrated into a CMOS process. An effective RESURF of the drain drift region enables a high breakdown voltage of about 90V and GHz operation. The measured output power density is 1.4W/mm at 1GHz for a supply voltage of 70V. A power added efficiency (PAE) of 51% and an output power density of 1.2W/mm was obtained at 50V.

Key concepts: LDMOS, Electrical engineering, Power semiconductor device, Transistor, Breakdown voltage, Materials science, Voltage, Power MOSFET

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