Implementation of AES encoder using active-HDL

With the ever-increasing growth of data communication, the need for security and privacy has become a strong necessity. AES is a symmetric block cipher that is intended to replace DES as the approved standard for wide range of applications. Numbers of hardware techniques have been developed for implementation of AES algorithm. In this paper we are using Active HDL (a third party tool) for the simulation development of AES algorithm encoder based on block RAM feature in FPGA chip. The simulation results are obtained for 128 bit or more than 128 bits of data block with improved throughput and reduced execution time as compared to previous simulation tools.