An automated layout-aware design flow

In analog integrated circuit design, it has always been necessary to improve the designer's productivity. The iterations between the electrical and physical synthesis, required to correct deviations due to parasitics, do degrade that productivity. The inclusion of the physical implementation directly within the electrical synthesis process, would in principle remove many or all of these iterations. This paper presents a fully-automated layout-aware design flow, whose key aspects are: (1) it uses commercially available tools and platforms to attain a highly integrated solution, (2) it provides solutions in the form of Pareto-optimal fronts, which represent the circuit's valuable trade-offs (and can be used in modern design flows), and (3) it allows including the impact of parasitics right into the fronts. This paper details the necessary tools and their integration for automation of the design flow and provides several examples of its use.