The effects of gate oxide short in 6-transistors SRAM cell
Abu Khari A’ain, K.S. Sim, Cheow Kwee Siong
Abstract
Abu Khari A’ain, K.S. Sim, Cheow Kwee Siong
Abstract
The effects of gate oxide short (GOS) in a single 6-MOS transistors SRAM cell are studied in this work, through SPICE simulation. Both uni-directional split model and bi-dimensional lumped-transistors model are used to model the GOS in NMOS for comparison. It is assumed that only one NMOS is defective at a time. TSMC 0.18/spl mu/m process parameters are used in the SPICE simulations. Interesting findings and results showed that GOS may leave catastrophic impacts on SRAM operations.
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The effects of gate oxide short (GOS) in a single 6-MOS transistors SRAM cell are studied in this work, through SPICE simulation. Both uni-directional split model and bi-dimensional lumped-transistors model are used to model the GOS in NMOS for comparison. It is assumed that only one NMOS is defective at a time. TSMC 0.18/spl mu/m process parameters are used in the SPICE simulations. Interesting findings and results showed that GOS may leave catastrophic impacts on SRAM operations.
Key concepts: NMOS logic, Spice, Static random-access memory, Transistor, Materials science, Electronic engineering, Electrical engineering, Computer science