A read-assist write-back voltage sense amplifier for low voltage-operated SRAMs

SoCs yield in nanometer CMOS technologies is largely governed by SRAM reliability. Sense amplifier (SA) is a crucial component in an SRAM macro. Mismatch variation in conventional SAs can cause SRAM read failure. The problem becomes worst when the SRAM array operates at low voltage. In this work we propose a timing-insensitive SA scheme featuring read-assist and write-back mechanisms. Carried out Monte Carlo simulations on a 500 mV typical 6T-SRAM column confirm the robustness of the proposed SA against up to 5σ mismatch variations. Owing to its read-assist feature, the proposed scheme offers 38% improvement in bitline differential voltage and 40% reduction in cell data level degradation.