2013Unpublished venueRequires access

A high dynamic range programmable gain amplifier for HomePlug AV powerline communication system

Szu-Yao Hung, Kai-Hsiang Chan, Charlie Chung‐Ping Chen

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Abstract

A high dynamic range programmable gain amplifier (PGA) for HomePlug AV powerline communication (PLC) receivers has been designed in a standard 0.18-μm CMOS technology. Linear transconductance amplifiers are employed as gain cells to obtain high dynamic range. A current compensation technique is proposed to achieve fine gain step characteristics. For constant settling time issue in automatic gain control (AGC) loop, a pseudo-exponential approximation is adopted. A 6-bit PGA suited for PLC receiver is realized by cascading PGA gain cell along with fixed gain amplifiers. The proposed PGA has been measured to exhibits a 3-dB bandwidth of more than 78 MHz and a dB-linear gain ranging from -24 to 74 dB with a maximum gain error of 0.24LSB. The core circuit consumes 1.9 mW through a 1.8 V supply, and occupies only 0.03 mm2active area.

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What this paper is about

A high dynamic range programmable gain amplifier (PGA) for HomePlug AV powerline communication (PLC) receivers has been designed in a standard 0.18-μm CMOS technology. Linear transconductance amplifiers are employed as gain cells to obtain high dynamic range. A current compensation technique is proposed to achieve fine gain step characteristics. For constant settling time issue in automatic gain control (AGC) loop, a pseudo-exponential approximation is adopted. A 6-bit PGA suited for PLC receiver is realized by cascading PGA gain cell along with fixed gain amplifiers. The proposed PGA has been measured to exhibits a 3-dB bandwidth of more than 78 MHz and a dB-linear gain ranging from -24 to 74 dB with a maximum gain error of 0.24LSB. The core circuit consumes 1.9 mW through a 1.8 V supply, and occupies only 0.03 mm2active area.

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Available abstract

A high dynamic range programmable gain amplifier (PGA) for HomePlug AV powerline communication (PLC) receivers has been designed in a standard 0.18-μm CMOS technology. Linear transconductance amplifiers are employed as gain cells to obtain high dynamic range. A current compensation technique is proposed to achieve fine gain step characteristics. For constant settling time issue in automatic gain control (AGC) loop, a pseudo-exponential approximation is adopted. A 6-bit PGA suited for PLC receiver is realized by cascading PGA gain cell along with fixed gain amplifiers. The proposed PGA has been measured to exhibits a 3-dB bandwidth of more than 78 MHz and a dB-linear gain ranging from -24 to 74 dB with a maximum gain error of 0.24LSB. The core circuit consumes 1.9 mW through a 1.8 V supply, and occupies only 0.03 mm2active area.

Key concepts: Automatic gain control, Programmable-gain amplifier, Open-loop gain, Dynamic range, Wide dynamic range, Amplifier, Electronic engineering, Variable-gain amplifier

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