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2011•EURASIP Journal on Wireless Communications and NetworkingOpen access

MAC and baseband processors for RF-MIMO WLAN

Zoran Stamenković, K. Tittelbach‐Helmrich, Miloš Krstić, J. Ibáñez, V́ıctor Elvira, Ignacio Santamarı́a

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Abstract

The article describes hardware solutions for the IEEE 802.11 medium access control (MAC) layer and IEEE 802.11a digital baseband in an RF-MIMO WLAN transceiver that performs the signal combining in the analogue domain. Architecture and implementation details of the MAC processor including a hardware accelerator and a 16-bit MAC-physical layer (PHY) interface are presented. The proposed hardware solution is tested and verified using a PHY link emulator. Architecture, design, implementation, and test of a reconfigurable digital baseband processor are described too. Description includes the baseband algorithms (the main blocks being MIMO channel estimation and Tx-Rx analogue beamforming), their FPGA-based implementation, baseband printed-circuit-board, and real-time tests.

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What this paper is about

The article describes hardware solutions for the IEEE 802.11 medium access control (MAC) layer and IEEE 802.11a digital baseband in an RF-MIMO WLAN transceiver that performs the signal combining in the analogue domain. Architecture and implementation details of the MAC processor including a hardware accelerator and a 16-bit MAC-physical layer (PHY) interface are presented. The proposed hardware solution is tested and verified using a PHY link emulator. Architecture, design, implementation, and test of a reconfigurable digital baseband processor are described too. Description includes the baseband algorithms (the main blocks being MIMO channel estimation and Tx-Rx analogue beamforming), their FPGA-based implementation, baseband printed-circuit-board, and real-time tests.

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Available abstract

The article describes hardware solutions for the IEEE 802.11 medium access control (MAC) layer and IEEE 802.11a digital baseband in an RF-MIMO WLAN transceiver that performs the signal combining in the analogue domain. Architecture and implementation details of the MAC processor including a hardware accelerator and a 16-bit MAC-physical layer (PHY) interface are presented. The proposed hardware solution is tested and verified using a PHY link emulator. Architecture, design, implementation, and test of a reconfigurable digital baseband processor are described too. Description includes the baseband algorithms (the main blocks being MIMO channel estimation and Tx-Rx analogue beamforming), their FPGA-based implementation, baseband printed-circuit-board, and real-time tests.

Key concepts: Baseband, PHY, Computer science, Transceiver, MIMO, Physical layer, Field-programmable gate array, Computer hardware

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