A Low Power Fast Ethernet Physical Layer Transceiver
Simon Buhr, Xin Xu, Martin Kreißig, Frank Ellinger
Abstract
Simon Buhr, Xin Xu, Martin Kreißig, Frank Ellinger
Abstract
This work presents the design of a low power Fast Ethernet physical layer (PHY) transceiver. The PHY chip is implemented in a 180 nm technology of GLOBALFOUNDRIES and optimized for lowest power consumption. Measurement results demonstrate error free data transmission with 100 Mb/s over up to 100 m category 5 unshielded twisted pair cables. Under full link utilization using a 100 m cable, the power consumption is only 70 mW. This is, to the best of the authors knowledge, the lowest power consumption reported to date for such a Fast Ethernet PHY transceiver.
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This work presents the design of a low power Fast Ethernet physical layer (PHY) transceiver. The PHY chip is implemented in a 180 nm technology of GLOBALFOUNDRIES and optimized for lowest power consumption. Measurement results demonstrate error free data transmission with 100 Mb/s over up to 100 m category 5 unshielded twisted pair cables. Under full link utilization using a 100 m cable, the power consumption is only 70 mW. This is, to the best of the authors knowledge, the lowest power consumption reported to date for such a Fast Ethernet PHY transceiver.
Key concepts: PHY, Transceiver, Ethernet, Physical layer, Synchronous Ethernet, Carrier Ethernet, Ethernet over SDH, Power consumption