VLSI Digital PSK Demodulator for Space Communication

Abstract This paper describes the design of a BPSK/QPSK demodulator implemented using multi‐rate digital signal processing in a CMOS ASIC. The demodulator is fully programmable via serial and parallel interfaces and handles symbol rates from 125 sym/s to 4 Msym/s. It performs at less than 0.5dB degradation from ideal BER vs. Eh IN characteristic. The system design considerations lead to the choice of a complex IF scheme with sampling at four times the intermediate frequency and a combined analog and digital matched filtering based on the pulselet concept. Signal processing algorithms include Costas carrier phase error detector, Zero‐Crossing Detector for timing error and algorithms for lock detection and loop filtering. Simulations of the entire demodulator including the ASIC part is accomplished by proprietary software. The ASIC is manufactured in a radiation tolerant 1 μm CMOS gate array process using 34085 gates. The main application area is spaceborne coherent TT&C transponders. The ASIC will fly on SPOT‐4 in 1994 as a part of the Experimental 5‐Band Transponder.