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A robust parallel DFE using extended LMS

Alan Gatherer, T.H. Meng

Open publisher page 2 citations

Abstract

A parallelizable ADFE (adaptive decision feedback equalizer) is presented which performs at an error rate close to that of the serial DFE. The complexity of the parallel architecture grows linearly with the speedup, with the constant of growth being unity. This allows for parallelization of the DFE to a reasonable level without a prohibitive increase in complexity. The complexity of each section of the parallel DFE is on the order of s/sup 2/ where s is the number of taps in the serial DFE. For a serial DFE the complexity is of order s. Therefore, for a speedup of T, one requires a hardware complexity that is on the order sT times that of the serial DFE. The increase in complexity is therefore linear in both speedup and number of taps.>

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What this paper is about

A parallelizable ADFE (adaptive decision feedback equalizer) is presented which performs at an error rate close to that of the serial DFE. The complexity of the parallel architecture grows linearly with the speedup, with the constant of growth being unity. This allows for parallelization of the DFE to a reasonable level without a prohibitive increase in complexity. The complexity of each section of the parallel DFE is on the order of s/sup 2/ where s is the number of taps in the serial DFE. For a serial DFE the complexity is of order s. Therefore, for a speedup of T, one requires a hardware complexity that is on the order sT times that of the serial DFE. The increase in complexity is therefore linear in both speedup and number of taps.>

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Available abstract

A parallelizable ADFE (adaptive decision feedback equalizer) is presented which performs at an error rate close to that of the serial DFE. The complexity of the parallel architecture grows linearly with the speedup, with the constant of growth being unity. This allows for parallelization of the DFE to a reasonable level without a prohibitive increase in complexity. The complexity of each section of the parallel DFE is on the order of s/sup 2/ where s is the number of taps in the serial DFE. For a serial DFE the complexity is of order s. Therefore, for a speedup of T, one requires a hardware complexity that is on the order sT times that of the serial DFE. The increase in complexity is therefore linear in both speedup and number of taps.>

Key concepts: Speedup, Parallelizable manifold, Computer science, Parallel computing, Computational complexity theory, Parallel algorithm, Algorithm

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