Parallelization of hydrocodes on the Intel Hypercube: Part 2

In a previous report (EGG-SPAG-7682, April 1987) we described the first results of our computational experiments on the Intel iPSC-286 (a 32 node hypercube with nodes based on the 80286/80287 chip) with certain algorithms for concurrent computational continuum dynamics. The first results were disappointing: the best speedup factors were less than 4 out of a possible 32. Modifications of our earlier algorithms to better fit the iPSC architecture led to significant improvement: the best speedup factors on these improved algorithms are now in excess of 24 out of 32. The earlier parallel algorithms had speedup efficiencies of 90% or better on several other parallel processors, namely, the HEP, ELXSI/10, and CRAY X-MP/4. These machines handled the global communications requird by the earlier parallel algorithms more efficiently than the iPSC. The algorithmic modifications yielding the greatest speedup factor improvements reduced the amount of communications relative to the amount of computations. 11 refs., 1 tab.