A Novel Delay Model of CMOS VLSI Circuits

In this paper, a piecewise linear delay model which can predict the accurate propagation delay of the general CMOS VLSI circuitry is presented. The model takes into account the effect of the slope of the input waveform on the delay. By using simple piecewise linear current model and piecewise linear channel charge storage model, it is possible to simulate the modern digital logic circuits in a reasonable amount of time. Excellent agreement with SPICE simulation has been observed in CMOS inverter and 2-input NAND gate cases.