Tradeoff between delay and area in gate sizing using Geometric Programming

A study about the tradeoff between delay and area (power) is presented in this work considering circuit gate sizing. We use a gate sizing tool based on Geometric Programming (GP), where delay is calculated by Elmore delay model. The optimization can be done targeting both delay and area (power) minimization. Tests were performed mapping ISCAS'85 benchmark circuits for 45nm technology. First, circuits were mapped to a typical standard cell library. Then, the gate sizing targeting delay minimization was performed. After, the circuits were sized targeting area considering a delay constraint. Three different delay constraints were considered, the minimum delay given by delay optimization and this minimum delay relaxed by 1% and by 5%. The energy/delay gain (EDG) metric was used to quantify the most efficient tradeoff. Considering the minimum delay, area (power) was reduced in 28.2%, on average. Area (power) was reduced in 41.7%, on average, when the delay was relaxed by 1% and the EDG metric was 41.7. Relaxing delay by 5%, was able to reduce area in 51%, on average, and EDG metric was 10.2.