A high speed low noise CMOS dynamic full adder cell

A new low power dynamic CMOS one bit full adder cell is presented. In this design technique is based on semi-domino logic. This new cell is compared with some previous proposed widely used dynamic adders as well as other conventional architectures. Objective of this work is to inspect the power, delay, power-delay-product and leakage performance of low voltage full adder cells in different CMOS logic styles. The proposed style gets its benefit in terms of power, delay, PDP, and noise tolerance. The performance of the full adder circuits is based on UMC 180nm CMOS process models at the supply voltage of 1.8V evaluated by the comparison of the simulation results obtained from Cadence.