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A multiple delay simulator for MOS LSI circuits

H. N. Nham, Ajoy K. Bose

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Abstract

This paper describes a multiple delay simulator for MOS LSI circuits. The basic primitives for this simulator are MOS transistor structures where the transistors are evaluated logically. Integer rise and fall delays are associated with each transition and these delays are computed automatically based on device characteristics and circuit capacitances. The simulator has been extensively used for the design verification of production LSI chips.

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What this paper is about

This paper describes a multiple delay simulator for MOS LSI circuits. The basic primitives for this simulator are MOS transistor structures where the transistors are evaluated logically. Integer rise and fall delays are associated with each transition and these delays are computed automatically based on device characteristics and circuit capacitances. The simulator has been extensively used for the design verification of production LSI chips.

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OpenAlex reports 49 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

This paper describes a multiple delay simulator for MOS LSI circuits. The basic primitives for this simulator are MOS transistor structures where the transistors are evaluated logically. Integer rise and fall delays are associated with each transition and these delays are computed automatically based on device characteristics and circuit capacitances. The simulator has been extensively used for the design verification of production LSI chips.

Key concepts: Computer science, Electronic circuit simulation, Electronic circuit, Transistor, Computer architecture simulator, Simulation, Logic simulation, Electronic engineering

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