An effective fault ordering heuristic for SAT-based dynamic test compaction techniques

Abstract Each chip is subjected to a post-production test after fabrication. A set of test patterns is applied to filter out defective devices. The size of this test set is an important issue. Generally, large test sets increase the test costs. Therefore, test compaction techniques are applied to obtain a compact test set. The effectiveness of these technique is significantly influenced by fault ordering. This paper describes how information about hard-to-detect faults can be extracted from an untestable identification phase and be used to develop a fault ordering technique which is able to reduce the pattern counts of highly compacted test sets generated by a SAT-based dynamic test compaction approach.