Design of high-speed low-power clock and data recovery circuit

In this thesis, the design of fully integrated high-speed low-power clock and data recovery (CDR) circuits in complementary metal-oxide-semiconductor (CMOS) devices for synchronous optical network (SONET) applications has been explored.The majority of the backbone optical communication systems are based on the SONET standards.The "SONET OC-192 Specifications" have been defined for 10-Gb/s optical communication applications in order to evaluate the jitter performance of the designs.Despite the aggressive device scaling in CMOS technology, the CDR circuits that are realized in CMOS processes still face significant high-frequency design and speed constraints.When it comes to complying with the stringent jitter requirements posed by the OC-192 standards, CMOS circuits have to work harder than their GaAs or SiGe counterparts to overcome the limitations due to the high-frequency parasitics.Extensive research work must be carried out at all fronts related to the CMOS CDRs in order to obtain a total solution to the problems currently faced by the designers.To contribute to the pool of these solutions, we have proposed several modifications and methods in this thesis.Before going into the detailed discussion, we should note that all the design work presented here is done on the phase-locked loop (PLL)-based CDR architectures and their building blocks.