2005•Unpublished venueRequires access
Fully-Differential 13 Gbps Clock Recovery Circuit for OC-255 SONET Applications
Wen Tsern Ho, Mourad N. El-Gamal
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Abstract
A fully differential, quasi-mixer based, half-rate clock recovery PLL has been implemented in a 0.18-/spl mu/m CMOS technology, and is optimized for high-speed of operation at 13 Gbit/s. A special differential varactor tuning arrangement is used to provide a wide operating frequency range from 6.2 GHz to 7.2 GHz, with a power consumption of 69 mW.