Architecture of baseband modem board for IEEE802.11ad technology
Sung–Woo Choi, Ilgyu Kim, Jae-Min Ahn
Abstract
Sung–Woo Choi, Ilgyu Kim, Jae-Min Ahn
Abstract
60-GHz band is a popular choice of industry for wireless personal area networks, which will enable data rates in the order of giga-bps. IEEE 802.11ad working group has specified the PHY and MAC technology over 60GHz. This paper suggests a system level architecture to make a hardware evaluation board for the IEEE 802.11ad PHY. We will introduce the physical specification of the IEEE 802.11ad briefly and find the system requirements for the FPGA board. Then, we show configuration of functional block of PHY modem and efficient block partitioning for 3 FPGAs. Furthermore, the practical baseband board architecture is shown and implementation result is summarized. The proposed baseband modem board supplies Control PHY and Single-carrier PHY of IEEE802.11ad. It supports the maximum data rate of 2.3Gbps and is adaptable to ASIC solution providing data rate of 4.6Gbps. This paper will be useful when designing the system transmitting data at the speed of multi-giga bps.
OpenAlex reports 1 citations for this work. Citation counts describe recorded attention and do not establish research quality.
A contribution statement is not available in the OpenAlex record.
Method details are not available in the OpenAlex metadata.
Findings are not separately available in the OpenAlex metadata.
Limitations are not available in the OpenAlex metadata.
Application details are not available in the OpenAlex metadata.
60-GHz band is a popular choice of industry for wireless personal area networks, which will enable data rates in the order of giga-bps. IEEE 802.11ad working group has specified the PHY and MAC technology over 60GHz. This paper suggests a system level architecture to make a hardware evaluation board for the IEEE 802.11ad PHY. We will introduce the physical specification of the IEEE 802.11ad briefly and find the system requirements for the FPGA board. Then, we show configuration of functional block of PHY modem and efficient block partitioning for 3 FPGAs. Furthermore, the practical baseband board architecture is shown and implementation result is summarized. The proposed baseband modem board supplies Control PHY and Single-carrier PHY of IEEE802.11ad. It supports the maximum data rate of 2.3Gbps and is adaptable to ASIC solution providing data rate of 4.6Gbps. This paper will be useful when designing the system transmitting data at the speed of multi-giga bps.
Key concepts: Baseband, PHY, Computer science, Field-programmable gate array, Application-specific integrated circuit, Wireless, Block (permutation group theory), Embedded system